NXP Semiconductors /MIMXRT1052 /ADC_ETC /TRIG1_CTRL

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Interpret as TRIG1_CTRL

31282724232019161512118743000000000000000000000000000000000000000000 (SW_TRIG)SW_TRIG0 (TRIG_MODE)TRIG_MODE0TRIG_CHAIN0TRIG_PRIORITY0 (SYNC_MODE)SYNC_MODE

Description

ETC_TRIG1 Control Register

Fields

SW_TRIG

Software write 1 as the TRIGGER. This register is self-clearing.

TRIG_MODE

TRIG mode register. 1’b0: hardware trigger. 1’b1: software trigger.

TRIG_CHAIN

TRIG chain length to the ADC. 0: Trig length is 1; … 7: Trig length is 8;

TRIG_PRIORITY

External trigger priority, 7 is highest, 0 is lowest .

SYNC_MODE

TRIG mode control . 1’b0: Disable sync mode; 1’b1: Enable sync mode

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